Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
A switch architecture and signal synchronization for GALS system-on-chips
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Proceedings of the 7th ACM international conference on Computing frontiers
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
A self-adaptable distributed DFS scheme for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Proceedings of the 4th International Workshop on Network on Chip Architectures
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
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The distribution of a synchronous clock in System-on- Chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the Globally Asynchronous, Locally Synchronous try to solve this issue by partitioning the SoC into isolated synchronous islands. This paper describes the bi-synchronous FIFO used on the DSPIN Network-on- Chip capable to interface systems working with different clock signals (frequency and/or phase). Its interfaces are synchronous and its architecture is scalable and synthesizable in synchronous standard cells. The metastability situations and its latency are analyzed. Its throughput, maximum frequency, and area are evaluated in function of the FIFO depth.