NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Integration, the VLSI Journal
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
RunAssert: a non-intrusive run-time assertion for parallel programs debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
VAPRES: a virtual architecture for partially reconfigurable embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
Asynchronous protocol converters for two-phase delay-insensitive global communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modified bundled-data as a new protocol for NoC asynchronous links
Microelectronics Journal
Analog Integrated Circuits and Signal Processing
Power modeling of a noc based design for high speed telecommunication systems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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In this paper, we propose the design of On-chip and Off-chip Interfaces adapted to a Globally Asynchronous Locally Synchronous (GALS) Network-on-Chip (NoC) architecture. The proposed On-chip interface not only handles the resynchronization between the synchronous and asynchronous NoC domains, but also implements NoC communication priorities. This design is based on existing multi-clock synchronization fifos based on Gray code, and is adapted to standard implementation tools. Concerning Off-chip communications, a new concept of mixed synchronous/asynchronous dual mode NoC port is proposed as an efficient Off-chip NoC interface for NoCbased open-platform prototyping. These interfaces have been successfully implemented in a 0.13um CMOS technology.