Power-efficient delay-insensitive codes for data transmission
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
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Asynchronous interconnection paradigm in NoCs has attracted many system designers in the recent years, through its different possible implementation strategies. In this paper, we present a new insight on how to categorize asynchronous protocols and explore a suitable protocol for the NoC asynchronous links. The new categorization criterion is based on the type of dependency between data transferring and handshaking tasks in a protocol. Furthermore, a new protocol called modified bundled-data (MBD) is introduced. MBD is a bundled-data-like protocol with two pairs of two-phase dual-rail encoded parity lines on the lateral sides of data lines, besides one two-phase acknowledgement line. The new protocol is evaluated by comparing its simulation results with those of bundled-data (BD) and dual-rail (DR) protocols on a 32-bit flit NoC asynchronous link. For this purpose, a new comprehensive interconnect model has been developed. The simulation results show that the new protocol's features such as power consumption, throughput, and latency are comparable with BD protocol's, while its signal integrity features are close to DR's.