Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
OCCN: A Network-On-Chip Modeling and Simulation Framework
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Micro
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Serialized asynchronous links for NoC
Proceedings of the conference on Design, automation and test in Europe
Flexible and abstract communication and interconnect modeling for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A case study for NoC-based homogeneous MPSoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
A thermal-aware application specific routing algorithm for network-on-chip design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Modified bundled-data as a new protocol for NoC asynchronous links
Microelectronics Journal
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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As embedded computing evolves towards ever more pow- erful architectures, the challenge of properly interconnect- ing large numbers of on-chip computation blocks is becom- ing prominent. Networks-on-Chip (NoCs) have been pro- posed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold. This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC de- sign in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis.