A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Design and Implementation in 65nm Technology
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Proceedings of the conference on Design, automation and test in Europe
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Circuits and Systems II: Express Briefs
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
Mesochronous NoC technology for power-efficient GALS MPSoCs
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Modified bundled-data as a new protocol for NoC asynchronous links
Microelectronics Journal
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NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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Journal of Systems Architecture: the EUROMICRO Journal
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ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi-application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130nm technology is carried out in terms of area, throughput, packet latency, and power consumption.