Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

Authors:
Daniele Ludovici;Alessandro Strano;Davide Bertozzi;Luca Benini;Georgi N. Gaydadjiev
Affiliations:
Computer Engineering Lab., Delft University of Technology, The Netherlands;ENDIF, University of Ferrara, 44100, Italy;DEIS, University of Bologna, 40136, Italy;Computer Engineering Lab., Delft University of Technology, The Netherlands;Computer Engineering Lab., Delft University of Technology, The Netherlands
Venue:
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Year:
2009

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Abstract

With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC setting are still largely uncovered. Most schemes are in fact placed between communicating switches, thus neglecting the abrupt increase of buffering resources needed at switch input stages. This paper goes a step forward and aims at deep integration of the synchronizer in the switch architecture, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. This paper compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters.