Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

Authors:
Daniele Ludovici;Alessandro Strano;Davide Bertozzi
Affiliations:
Computer Engineering Lab., TUDelft, Delft, The Netherlands;University of Ferrara, Ferrara, Italy;University of Ferrara, Ferrara, Italy
Venue:
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Year:
2009

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Abstract

This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integration of GALS synchronization interfaces into NoC architecture building blocks. At the cost of re-engineering the input/output stages of NoC switches and network interfaces, this approach proves capable of materializing GALS NoCs with the same area and power of their synchronous counterparts, while reducing latency at the clock domain boundary. This design style is experimented in this paper with a mesochronous synchronizer and a dual-clock FIFO, which are tightly coupled with the switches of the xpipesLite NoC architecture.