Proceedings of the conference on Design, automation and test in Europe - Volume 1
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
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Self-timed mesochronous interconnection scheme is presented for the interface between synchronous modules. It consists of a self-timed FIFO and a local clock control circuit placed between synchronous modules. The self-timed FIFO receives a data stream and holds it until the Jirst data is synchronized at the receiving module. After the synchronization, the clock input to the receiving module is available through the local clock control circuit. Theinterconnection scheme operates regardless of the amount of the clock skew between the modules. An experimental design is presented that demonstrates the validity of the method.