Timing closure through a globally synchronous, timing partitioned design methodology

Authors:
Anders Edman;Christer Svensson
Affiliations:
Linköping University, Linköping, Sweden;Linköping University, Linköping, Sweden
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 6
Cited 10

Performance of Synchronous and Asynchronous Schemes for VLSI Systems

IEEE Transactions on Computers
Getting to the bottom of deep submicron

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Digital systems engineering

Digital systems engineering
A methodology for correct-by-construction latency insensitive design

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Proceedings of the 38th annual Design Automation Conference
Addressing the timing closure problem by integrating logic optimization and placement

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Æthereal Network on Chip: Concepts, Architectures, and Implementations

IEEE Design & Test
The impact of the nanoscale on computing systems

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Budgeting-free hierarchical design method for large scale and high-performance LSIs

Proceedings of the 43rd annual Design Automation Conference
Synchronous elastic circuits with early evaluation and token counterflow

Proceedings of the 44th annual Design Automation Conference
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

Proceedings of the 2nd International Workshop on Network on Chip Architectures
SSMCB: low-power variation-tolerant source-synchronous multicycle bus

IEEE Transactions on Circuits and Systems Part I: Regular Papers
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs

Integration, the VLSI Journal
Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors

Journal of Parallel and Distributed Computing
A Scheduling Strategy for Synchronous Elastic Designs

Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue

Quantified Score

Hi-index	0.00

Visualization

Abstract

A method to mitigate timing problems due to global wire delays is proposed. The method follows closely a fully synchronous design flow and utilizes only true digital library elements. The design is partitioned into isochronous blocks at system level, where a few clock cycles latency is inserted between the isochronous blocks. This latency is then utilized to automatically mitigate unknown global wire delays, unknown global clock skews and other timing uncertainties occurring in backend design. The new method is expected to considerably reduce the timing closure effort in large high frequency digital designs in deep submicron technologies.