Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Hierarchical physical design methodology for multi-million gate chips
Proceedings of the 2001 international symposium on Physical design
Delay budgeting for a timing-closure-driven design method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A timing-driven module-based chip design flow
Proceedings of the 41st annual Design Automation Conference
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design flow and methodology for 50M gate ASIC
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.