Design planning for high-performance ASICs
IBM Journal of Research and Development
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Designing mega-ASICs in nanogate technologies
Proceedings of the 40th annual Design Automation Conference
Budgeting-free hierarchical design method for large scale and high-performance LSIs
Proceedings of the 43rd annual Design Automation Conference
Multi-core design automation challenges
Proceedings of the 44th annual Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Geometric quadrisection in linear time, with application to VLSI placement
Discrete Optimization
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There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40M gate ASICs are nearing tape-out, and 50M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development efforts focused on enabling ASIC and SoC designs of these sizes and complexity, centered around the reduction of design turn-around-time, improvement of the quality of results and the modeling and optimization of deep sub-micron electrical effects.