Max-balancing weighted directed graphs and matrix scaling
Mathematics of Operations Research
IEEE Transactions on Computers
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
S/390 parallel enterprise server generation 3: a balanced system and cache structure
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Applying Parallel Computation Algorithms in the Design of Serial Algorithms
Journal of the ACM (JACM)
A flat, timing-driven design system for a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A timing analysis algorithm for circuits with level-sensitive latches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
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The maximum mean weight cycle problem is well-known: given a digraph G with weights c:E(G) → R, find a directed circuit in G whose mean weight is maximum. Closely related is the minimum balance problem: Find a potential π: V(G) → R such that the numbers slack(e):=π(w)-π(v)-c((v, w))(e=(v, w)∈E(G)) are optimally balanced: for any subset of vertices, the minimum slack on an entering edge should equal the minimum slack on a leaving edge. Both problems can be solved by a parametric shortest path algorithm.We describe an application of these problems to the design of logic chips. In the simplest model, optimizing the clock schedule of a chip to minimize the cycle time is equivalent to a maximum mean weight cycle problem. It is very important to find a solution with well-balanced slacks; this problem, in the simple model, is a minimum balance problem.However, in practical situations many constraints have to be taken into account. Therefore minimizing the cycle time and finding the optimum slack distribution are more general problems. We show how a parametric shortest path algorithm can be extended to solve these problems efficiently.Computational results with recent IBM processor chips show that the cycle time reduces considerably. Moreover, the number of critical paths (with small slack) decreases dramatically. As a result we obtain significantly faster chips. The running time of our algorithm is reasonable even for very large designs.