The design of a microprocessor
The design of a microprocessor
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Design for testability and diagnosis in a VLSI CMOS System/370 processor
IBM Journal of Research and Development
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
A half-micron CMOS logic generation
IBM Journal of Research and Development - Special issue: IBM CMOS technology
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Circuit placement chip optimization, and wire routing for IBM IC technology
IBM Journal of Research and Development
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
S/390 parallel enterprise server generation 3: a balanced system and cache structure
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Timing analysis and optimization of a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
In the Driver's Seat of BooleDozer
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
S/390 parallel enterprise server generation 3: a balanced system and cache structure
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
| Hi-index | 0.00 |