Timing analysis and optimization of a high-performance CMOS processor chipset

Authors:
U. Fassnacht;J. Schietke
Affiliations:
IBM Entwicklung GmbH Boeblingen, Schoenaicher Str. 220, 71032 Boeblingen, Germany;Research Institute for Discrete Mathematics, University of Bonn, Nassestr. 2, 53113 Bonn, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

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Abstract

We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server - Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results.