RICE: Rapid interconnect circuit evaluator

AWESpice: a general tool for the accurate and efficient simulation of interconnect problems

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Generalized moment-matching methods for transient analysis of interconnect networks

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

On the stability of moment-matching approximations in asymptotic waveform evaluation

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

IPDA: interconnect performance design assistant

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Reliable non-zero skew clock trees using wire width optimization

DAC '93 Proceedings of the 30th international Design Automation Conference

Fast approximation of the transient response of Lossy Transmision Line Trees

DAC '93 Proceedings of the 30th international Design Automation Conference

S-parameter based macro model of distributed-lumped networks using exponentially decayed polynomial function

DAC '93 Proceedings of the 30th international Design Automation Conference

RC interconnect synthesis—a moment fitting approach

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Performance-driven simultaneous place and route for row-based FPGAs

DAC '94 Proceedings of the 31st annual Design Automation Conference

A gate-delay model for high-speed CMOS circuits

DAC '94 Proceedings of the 31st annual Design Automation Conference

Delay analysis of the distributed RC line

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Simultaneous gate and interconnect sizing for circuit-level delay optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Clock distribution design and verification for PowerPC microprocessors

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

A sequential quadratic programming approach to concurrent gate and wire sizing

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Coping with RC(L) interconnect design headaches

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Analytical delay models for VLSI interconnects under ramp input

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Clock Distribution Methodology for PowerPC™Microprocessors

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Lumped interconnect models via Gaussian quadrature

DAC '97 Proceedings of the 34th annual Design Automation Conference

Timing metrics for physical design of deep submicron technologies

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

ISPD '99 Proceedings of the 1999 international symposium on Physical design

AWE macromodels of VLSI interconnect for circuit simulation

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

FAR-DS: full-plane AWE routing with driver sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Equivalent Elmore delay for RLC trees

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

RLC interconnect delay estimation via moments of amplitude and phase response

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Timing analysis and optimization of a high-performance CMOS processor chipset

Proceedings of the conference on Design, automation and test in Europe

Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

Analog Integrated Circuits and Signal Processing

Fast analysis and optimization of power/ground networks

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Efficient model order reduction via multi-node moment matching

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Realizable RLCK circuit crunching

Proceedings of the 40th annual Design Automation Conference

Simple metrics for slew rate of RC circuits based on two circuit moments

Proceedings of the 40th annual Design Automation Conference

Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity

ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Delay Models for MCM Interconnects when Response is Non-Monotone

MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference

Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Crosstalk Aware Static Timing Analysis: A Two Step Approach

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Improved model-order reduction by using spacial information in moments

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Circuit-aware architectural simulation

Proceedings of the 41st annual Design Automation Conference

Variational delay metrics for interconnect timing analysis

Proceedings of the 41st annual Design Automation Conference

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Gate delay calculation considering the crosstalk capacitances

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Piece-wise approximations of RLCK circuit responses using moment matching

Proceedings of the 42nd annual Design Automation Conference

Computation of signal threshold crossing times directly from higher order moments

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Calculating the effective capacitance for the RC interconnect in VDSM technologies

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Expanding the frequency range of AWE via time shifting

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Non-gaussian statistical interconnect timing analysis

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Efficient computation of current flow in signal wires for reliability analysis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Integration, the VLSI Journal

A new algorithm for simultaneous gate sizing and threshold voltage assignment

Proceedings of the 2009 international symposium on Physical design

Slope interconnect effort: gate-interconnect interdependent delay modeling for early CMOS circuit simulation

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

IBM Journal of Research and Development

A new algorithm for simultaneous gate sizing and threshold voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An efficient delay metric on RC interconnects under saturated ramp inputs

ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV

Accurate current estimation for interconnect reliability analysis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

High-performance gate sizing with a signoff timer

Proceedings of the International Conference on Computer-Aided Design