Delay evaluation with lumped linear RLC interconnect circuit models
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0) on a time-shifted version of the original signal. As compared to other well-known techniques (such as AWE by Pillage and Rohrer, 1990), TSMM offers distinct advantages. The 50% delay and rise time are determined with much more accuracy for a given approximation order. Moreover, the solutions have significantly improved accuracy as compared to AWE, especially for moderate to highly inductive signals. TSMM is able to achieve the approximation capability of PVL (Feldmann and Freund, 1995) and PRIMA (Odabasioglu et al., 1998) with much lower approximation order.