Proceedings of the 38th annual Design Automation Conference
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2002 international symposium on Low power electronics and design
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Inductance Modeling for On-Chip Interconnects
Analog Integrated Circuits and Signal Processing
Transmission line design of clock trees
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing fast on-chip interconnects for deep submicrometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2004 international workshop on System level interconnect prediction
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simplified delay design guidelines for on-chip global interconnects
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
Proceedings of the 41st annual Design Automation Conference
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Layout techniques for on-chip interconnect inductance reduction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Accounting for the skin effect during repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
Piece-wise approximations of RLCK circuit responses using moment matching
Proceedings of the 42nd annual Design Automation Conference
Expanding the frequency range of AWE via time shifting
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Wire shaping of RLC interconnects
Integration, the VLSI Journal
An analysis of interconnect delay minimization by low-voltage repeater insertion
Microelectronics Journal
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach
Proceedings of the 20th annual conference on Integrated circuits and systems design
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A global interconnect link design for many-core microprocessors
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A fast general slew constrained minimum cost buffering algorithm
Microelectronics Journal
Low-power and high-performance techniques in global interconnect signaling
Microelectronics Journal
Minimize the delay of parasitic capacitance and modeling in RLC circuit
Proceedings of the 2009 International Conference on Hybrid Information Technology
Delay and power management of voltage-scaled repeater driven long interconnects
International Journal of Modelling and Simulation
Reducing signal timing variations in inter-core busses
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
High speed interconnect through device optimization for subthreshold FPGA
Microelectronics Journal
Evaluating carbon nanotube global interconnects for chip multiprocessor applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects
International Journal of Circuit Theory and Applications
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing
Microprocessors & Microsystems
Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects
Journal of Computational Electronics
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A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale.