Introduction to Grey system theory
The Journal of Grey System
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Planar-DME: a single-layer zero-skew clock tree router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven repeater block planning for interconnect-centric floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This study has demonstrated that the clock tree construction in an SoC should be expanded to consider the intrinsic delay and skew of each IP's clock sink. A novel algorithm, called GDME, is proposed to combine grey relational clustering and DME approach for solving the problem of clock tree construction. Grey relational analysis can cluster the best pair of clock sinks and that guide a tapping point search for a DME algorithm for constructing a clock tree with zero skew and minimal delay. Experimentally, the proposed algorithm always obtains an RC-or RLC-based clock tree with zero skew and minimal delay for all the test cases and benchmarks. Experimental results demonstrate that the GDME improves up to 3.74% for total average in terms of total wire length compared with other DME algorithms. Furthermore, our results for the zero-skew RLC-based clock trees compared with Hspice are 0.017% and 0.2% lower for absolute average in terms of skew and delay, respectively.