Introduction to algorithms
IEEE Transactions on Computers
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Planar-DME: a single-layer zero-skew clock tree router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for the zero-skew tree (ZST) [Edahiro 1992; Chao et al. 1992] and bounded-skew tree (BST) [Cong and Koh 1995; Huang et al. 1995; Kahng and Tsao 1997; Cong et al. 1998] routings; hence, the names UST/DME and Greedy-UST/DME for our UST algorithms. Our novel contribution is that we simultaneously perform skew scheduling and tree routing so that each local skew range is incrementally refined to a skew value that minimizes the wirelength increase during the bottom-up merging phase of DME. As a result, not only is the skew schedule feasible, but also the wirelength increase is minimized at each merging step of clock tree construction. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total routing wirelength.