Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
EURO-DAC '94 Proceedings of the conference on European design automation
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Development of FPGA based adaptive image enhancement filter system using genetic algorithms
CEC '02 Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02
Development of hybrid genetic algorithms for product line designs
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
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The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorithms for designing a clock network, the multi-level model of clock binary tree is built, and the binary tree construction algorithm of clock signal based on multi-level genetic algorithm (MLGA) is presented. The experiments on random test cases and standard benchmark test cases show that multi-level genetic algorithm can produce much better clock network design in most cases when compared with conventional heuristic algorithms.