Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal wire and transistor sizing for circuits with non-tree topology
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Digital systems engineering
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Gated clock routing minimizing the switched capacitance
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2001 international symposium on Physical design
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Minimum-buffered routing of non-critical nets for slew rate and reliability control
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
General framework for removal of clock network pessimism
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design of Resonant Global Clock Distributions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Impact of line edge roughness on the resistivity of nanometer-scale interconnects
Microelectronic Engineering - Proceedings of the European workshop on materials for advanced metallization 2004
Timing
Statistical Analysis of Clock Skew Variation in H-Tree Structure
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Clock trees: differential or single ended?
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel clock distribution and dynamic de-skewing methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Sensitivity evaluation of global resonant H-tree clock distribution networks
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Giga-hertz rate single slope conversion technique with 512-phase RTWO
Analog Integrated Circuits and Signal Processing
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Practical Clock Tree Robustness Signoff Metrics
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A novel scheme to reduce short-circuit power in mesh-based clock architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
Proceedings of the 2009 international symposium on Physical design
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Skew management of NBTI impacted gated clock trees
Proceedings of the 19th international symposium on Physical design
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Characterizing processor thermal behavior
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Timing-driven variation-aware nonuniform clock mesh synthesis
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Clocking in Modern VLSI Systems
Clocking in Modern VLSI Systems
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Non-uniform clock mesh optimization with linear programming buffer insertion
Proceedings of the 47th Design Automation Conference
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
3-D stacked die: now or future?
Proceedings of the 47th Design Automation Conference
A Mesh-Buffer Displacement Optimization Strategy
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Contango: integrated optimization of SoC clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of NBTI induced clock skew in gated clock trees
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Speed Clock Network Design
High-Speed Clock Network Design
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus
Proceedings of the International Conference on Computer-Aided Design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
A methodology for local resonant clock synthesis using LC-assisted local clock buffers
Proceedings of the International Conference on Computer-Aided Design
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
High-performance clock mesh optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
Post-processing of clock trees via wiresizing and buffering for robust design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EWA: efficient wiring-sizing algorithm for signal nets and clock nets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Efficiency Green Function-Based Thermal Simulation Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
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High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.