Full-chip thermal analysis for the early design stage via generalized integral transforms
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Addressing thermal and power delivery bottlenecks in 3D circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate temperature estimation using noisy thermal sensors
Proceedings of the 46th Annual Design Automation Conference
Processor speed control with thermal constraints
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On-chip sensor-driven efficient thermal profile estimation algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A linear-time approach for the transient thermal simulation of liquid-cooled 3d ics
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Proceedings of the International Conference on Computer-Aided Design
Fast Poisson solvers for thermal analysis
Proceedings of the International Conference on Computer-Aided Design
Fast poisson solvers for thermal analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NUMANA: a hybrid numerical and analytical thermal simulator for 3-D ICs
Proceedings of the Conference on Design, Automation and Test in Europe
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.03 |
Due to technology scaling trends, the accurate and efficient calculations of the temperature distribution corresponding to a specific circuit layout and power density distribution will become indispensable in the design of high-performance very large scale integrated circuits. In this paper, we present three highly efficient thermal simulation algorithms for calculating the on-chip temperature distribution in a multilayered substrate structure. All three algorithms are based on the concept of the Green function and utilize the technique of discrete cosine transform. However, the application areas of the algorithms are different. The first algorithm is suitable for localized analysis in thermal problems, whereas the second algorithm targets full-chip temperature profiling. The third algorithm, which combines the advantages of the first two algorithms, can be used to perform thermal simulations where the accuracy requirement differs from place to place over the same chip. Experimental results show that all three algorithms can achieve relative errors of around 1% compared with that of a commercial computational fluid dynamic software package for thermal analysis, whereas their efficiencies are orders of magnitude higher than that of the direct application of the Green function method.