VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Proceedings of the 30th annual international symposium on Computer architecture
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-story power delivery for supply noise reduction and low voltage operation
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 international symposium on Low power electronics and design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IC thermal simulation and modeling via efficient multigrid-based approaches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Efficiency Green Function-Based Thermal Simulation Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a critical issue in today's VLSI designs, especially for 3D IC technologies. To alleviate the pin limitation problem, a stacked-Vdd circuit paradigm has recently been proposed in the literature. However, for a circuit designed using this paradigm, a significant amount of power may be wasted if modules are not carefully assigned to different Vdd domains. In this article, we present a partition-based algorithm for efficiently assigning modules at the floorplanning level, so as to reuse currents between Vdd domains and minimize the power wasted during the operation of the circuit. Experimental results on both 3D and 2D ICs show that compared with assigning modules to different Vdd domains using enumeration and simulated annealing, our algorithm can generate circuits with competitive power and IR noise performance, while being orders of magnitude faster.