Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Designing cad tools for reconfigurable computing
Designing cad tools for reconfigurable computing
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Peak temperature control and leakage reduction during binding in high level synthesis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
How does partitioning matter for 3D floorplanning?
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Block alignment in 3D floorplan using layered TCG
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Systematic temperature sensor allocation and placement for microprocessors
Proceedings of the 43rd annual Design Automation Conference
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 2006 international symposium on Low power electronics and design
Thermal-aware high-level synthesis based on network flow method
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Thermal monitoring mechanisms for chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Multidisciplinary heat generating logic block placement optimization using genetic algorithm
Microelectronics Journal
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Designing a 3-D FPGA: switch box architecture and thermal issues
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
Integration, the VLSI Journal
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Addressing thermal and power delivery bottlenecks in 3D circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A criticality-driven microarchitectural three dimensional (3D) floorplanner
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Circuits and Systems II: Express Briefs
Integration, the VLSI Journal
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
System-level process variability analysis and mitigation for 3D MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
TABS: temperature-aware layout-driven behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Thermal signature: a simple yet accurate thermal index for floorplan optimization
Proceedings of the 48th Design Automation Conference
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
System-level design space exploration for three-dimensional (3D) SoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Application-specific temperature reduction systematic methodology for 2d and 3d networks-on-chip
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Chemical-mechanical polishing aware application-specific 3D NoC design
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast fixed-outline 3-D IC floorplanning with TSV co-placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New heuristic algorithms for low-energy mapping and routing in 3D NoC
International Journal of Computer Applications in Technology
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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As the technology progresses, interconnect delays have become bottlenecks of chip performance. 3D integrated circuits are proposed as one way to address this problem. However, thermal problem is a critical challenge for 3D IC circuit design. We propose a thermal-driven 3D floorplanning algorithm. Our contributions include: (1) a new 3D floorplan representation, CBA and new interlayer local operations to more efficiently exploit the solution space; (2) an efficient thermal-driven 3D floorplanning algorithm with an integrated compact resistive network thermal model (CBA-T); (3) two fast thermal-driven 3D floorplanning algorithms using two different thermal models with different runtime and quality (CBA-T-Fast and CBA-T-Hybrid). Our experiments show that the proposed 3D floorplan algorithm with CBA representation can reduce the wirelength by 29% compared with a recent published result from (Hsiu et al., 2004). In addition, compared to a nonthermal-driven 3D floorplanning algorithm, the thermal-driven 3D floorplanning algorithm can reduce the maximum on-chip temperature by 56%.