System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Simulated Annealing: Searching for an Optimal Temperature Schedule
SIAM Journal on Optimization
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Application exploration for 3-d integrated circuits: TCAM, FIFO, and FFT case studies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Proceedings of the International Conference on Computer-Aided Design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The introduction of 3D chip architectures is an increasingly attractive integration solution due to the potential performance improvement, power consumption reduction and heterogeneous integration. Nevertheless, thermal distribution, evacuation and limitation constitute some of the key issues that can hinder widespread adoption of 3D integration technology. Efficient 3D floorplan algorithms have to be developed to address such complexity. In this paper we first discuss the implementation of such an algorithm and identify parameters that play a role in the solution quality. We then propose the use of a genetic algorithm to discover sets of parameters that guarantee good @?oorplan quality. Then, we present an improved thermal-aware @?oorplanner based on a new formulation of the cost function that minimizes not only peak temperature, but also thermal gradients. The temperature minimization goal is reinforced using a smart heuristic that guides 3D moves in the direction of placing power hungry blocks next to the heat sink. Experimental results show the ability of the method to reduce the temperature peak and gradient signi@?cantly, while maintaining area, wirelength and computation time.