Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Three-dimensional Optoelectronic Architectures for Massively Parallel Processing Systems
MPPOI '97 Proceedings of the 4th International Conference on Massively Parallel Processing Using Optical Interconnections
Global interconnect design in a three-dimensional system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2005 international workshop on System level interconnect prediction
Interconnect delay minimization through interlayer via placement in 3-D ICs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
IBM Journal of Research and Development - POWER5 and packaging
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
3D-softchip: a novel architecture for next-generation adaptive computing systems
EURASIP Journal on Applied Signal Processing
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Rethinking the wirelength benefit of 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9 x increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogenous gigascale intergrated circuits.