Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Beyond Moore's Law: The Interconnect Era
Computing in Science and Engineering
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Silicon carrier for computer systems
Proceedings of the 43rd annual Design Automation Conference
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A multi-story power delivery technique for 3D integrated circuits
Proceedings of the 13th international symposium on Low power electronics and design
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-dimensional silicon integration
IBM Journal of Research and Development
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Proceedings of the 49th Annual Design Automation Conference
Effect of TSV fabrication technology on power distribution in 3D ICs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Voltage propagation method for 3-D power grid analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.