Module assignment for pin-limited designs under the stacked-Vdd paradigm

Authors:
Yong Zhan;Tianpei Zhang;Sachin S. Sapatnekar
Affiliations:
University of Minnesota;University of Minnesota;University of Minnesota
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

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Abstract

This paper addresses the module assignment problem in pin-limited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficiently assigning modules at the floorplanning level so as to reuse currents between the Vdd domains, and minimize the power wasted during the operation of the circuit. Experimental results on a DLX architecture show that compared with assigning modules to different Vdd rails using a bin-packing technique, the circuit generated by our algorithm has 32% lower wasted power, on average. In addition, experiments on a 3D IC example show that our module assignment approach is equally effective in reducing the power waste in 3D ICs.