Silicon carrier for computer systems

Authors:
Chirag S. Patel
Affiliations:
IBM T. J. Watson Research Center, Yorktown Heights, NY
Venue:
Proceedings of the 43rd annual Design Automation Conference
Year:
2006

Citing 3
Cited 3

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Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

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Interconnect opportunities for gigascale integration

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Three-dimensional silicon integration

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Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

System-on-Package (SOP) based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. This paper describes the electrical characterization of key technical elements of the silicon carrier and discusses the significance of those elements in enhancing the overall system performance. The paper also discusses some methodologies that may allow silicon carrier technical elements to be easily integrated within existing EDA tools.