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IBM Journal of Research and Development
Laser release process to obtain freestanding multilayer metal-polyimide circuits
IBM Journal of Research and Development - Special issue: optical lithography I
System on Chip or System on Package?
IEEE Design & Test
An advanced multichip module (MCM) for high-performance UNIX servers
IBM Journal of Research and Development
The IBM ASIC/SoC methodology--A recipe for first-time success
IBM Journal of Research and Development
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Exploitation of optical interconnects in future server architectures
IBM Journal of Research and Development - POWER5 and packaging
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Architectural implications of brick and mortar silicon manufacturing
Proceedings of the 34th annual international symposium on Computer architecture
Why should we do 3D integration?
Proceedings of the 45th annual Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Three-dimensional silicon integration
IBM Journal of Research and Development
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
IBM Journal of Research and Development
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Thermomechanical modeling of 3D electronic packages
IBM Journal of Research and Development
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
Technologies for exascale systems
IBM Journal of Research and Development
3D transient thermal solver using non-conformal domain decomposition approach
Proceedings of the International Conference on Computer-Aided Design
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System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.