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Will Moore's Law Be Sufficient?
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Chip-Package Codesign Flow for Mixed-Signal SiP Designs
IEEE Design & Test
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Functionality-power-packaging considerations in context aware wearable systems
Personal and Ubiquitous Computing - Special Issue: Selected Papers of the ARCS06 Conference
High performance RF-microwave multilayer integrated components for wireless applications
EHAC'05 Proceedings of the 4th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Architectural tradeoffs in wearable systems
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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Electronics products of the future must be realized efficiently promising higher performance at lower cost within much shorter product design and upgrade cycles. ASIC foundries and EDA vendors see increasing VLSI integration capabilities as a promising new business opportunity through the System-on-Chip (SOC) paradigm that extends ASICs design from the component level to the system level. The systems integration community and electronics packaging design vendors see the systems market as an extension of their current business, the so-called Systems-on-Package (SOP) paradigm, and one that raises their role to new level of importance in the product supply chain linking electronics packaging directly to product specification, early design and ASIC design. Political issues aside, there exist technical, legal, and business challenges both paradigms must overcome to find broad-based acceptance. In the authors' opinion, the Systems-on-Package (SOP) paradigm promises a higher return on investment (ROI) at a much lower risk for the electronics products design, well into the new millenium.