Stochastic wire-length and delay distributions of 3-dimensional circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IBM Journal of Research and Development - POWER5 and packaging
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Three-dimensional silicon integration
IBM Journal of Research and Development
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs
Proceedings of the System Level Interconnect Prediction Workshop
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
Effect of TSV fabrication technology on power distribution in 3D ICs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
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Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We derive a new 3D wirelength distribution model considering TSV size. Based on this new prediction model, we explain the impact of several design parameters newly introduced in 3D ICs. We also present a case study to show how the model can help make early design decisions for 3D ICs.