Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study
Proceedings of the 46th Annual Design Automation Conference
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
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One of the most effective ways to deal with the area and capacitance overhead issues with through-silicon vias (TSVs) in 3D ICs is to reduce the size of TSVs themselves. Today, the diameter of the smallest TSV available is around 1 μm, and this is expected to reach sub-micron dimensions in a few years. This downscaling of TSVs requires research on the impact of nano-scale TSVs on the quality of 3D IC designs to provide academia and industry with the quantified effects. In this paper, we investigate, for the first time, the impact of nano-scale TSVs on the area, wirelength, delay, and power quality of today and future 3D IC designs. For our future process technology, we develop a 22nm standard cell and interconnect library. We also use four sets of TSV-related dimensions in our GDSII-level 3D IC layouts. Based on these resources, we present a thorough study on the impact of nano-scale TSVs on the design quality of today and future 3D ICs.