Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Stochastic wire-length and delay distributions of 3-dimensional circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study
Proceedings of the 46th Annual Design Automation Conference
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs
Proceedings of the System Level Interconnect Prediction Workshop
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Is TSV-based 3D integration suitable for inter-die memory repair?
Proceedings of the Conference on Design, Automation and Test in Europe
Pragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSV
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deflection routing in 3D network-on-chip with limited vertical bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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In this paper, we present a delay and power prediction model for buffered interconnects used in 3D ICs. The key idea is to model the impact of RC parasitics of Through-Silicon Vias (TSVs) used in 3D interconnects on delay and power consumption. Due to its large size compared with other layout objects such as metal wires, TSVs contain significant RC parasitics, which directly affect the overall delay and power of the wires that contain them. On the other hand, buffer insertion on TSV-based 3D interconnects is also non-trivial mainly because buffers as well as TSVs have non-trivial area overhead. In addition, both TSVs and buffers occupy device and M1 layers, thereby becoming layout obstacles to each other. Our interconnect model accurately captures the impact of both TSVs and buffers on 3D interconnects.