T3: Trends and Challenges in VLSI Technology Scaling towards 100nm
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
3D Integration: Technology and Applications
3D Integration: Technology and Applications
Architecture design exploration of three-dimensional (3D) integrated DRAM
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Roadmap for 22nm and beyond (Invited Paper)
Microelectronic Engineering
3D-Integrated SRAM Components for High-Performance Microprocessors
IEEE Transactions on Computers
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Nanoscale Memory Repair
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we address lower level issues related to 3D inter-die memory repair in an attempt to evaluate the actual potential of this approach for current and foreseeable technology developments. We propose several implementation schemes both for inter-die row and column repair and evaluate their impact in terms of area and delay. Our analysis suggests that current state-of-the-art TSV dimensions allow inter-die column repair schemes at the expense of reasonable area overhead. For row repair, however, most memory configurations require TSV dimensions to scale down at least with one order of magnitude in order to make this approach a possible candidate for 3D memory repair. We also performed a theoretical analysis of the implications of the proposed 3D repair schemes on the memory access time, which indicates that no substantial delay overhead is expected and that many delay versus energy consumption tradeoffs are possible.