Efficient spare allocation in reconfigurable arrays
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An efficient exact algorithm for constraint bipartite vertex cover
Journal of Algorithms
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
IEEE Design & Test
A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An O(v|v| c |E|) algoithm for finding maximum matching in general graphs
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
IBM Journal of Research and Development
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Journal of Electronic Testing: Theory and Applications
Is TSV-based 3D integration suitable for inter-die memory repair?
Proceedings of the Conference on Design, Automation and Test in Europe
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Three-dimensional (3D) memory products are emerging to fulfill the ever-increasing demands of storage capacity. In 3D-stacked memory, redundancy sharing between neighboring vertical memory blocks using short through-silicon vias (TSVs) is a promising solution for yield enhancement. Since different memory dies are with distinct fault bitmaps, how to selectively matching them together to maximize the yield for the bonded 3D-stacked memory is an interesting and relevant problem. In this paper, we present novel solutions to tackle the above problem. Experimental results show that the proposed methodology can significantly increase memory yield when compared to the case that we only bond self-reparable dies together.