Beyond the flow decomposition barrier
Journal of the ACM (JACM)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-dimensional silicon integration
IBM Journal of Research and Development
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
ICALP'06 Proceedings of the 33rd international conference on Automata, Languages and Programming - Volume Part I
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Proceedings of the Conference on Design, Automation and Test in Europe
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Proceedings of the Conference on Design, Automation and Test in Europe
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
| Hi-index | 0.00 |
3D-stacked ICs that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleaness of silicon dies, rendering prior TSV redundancy solutions less effective. To resolve this problem, we present a novel TSV repair framework, including a hardware architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, and the corresponding repair algorithm. By doing so, the manufacturing yield for 3D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.