A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Through Silicon Via (TSV) is the state-of-the-art vertical interconnect technology in three dimensional Integrated Circuits (3D-ICs). TSVs offer short wire length with low capacitive load and, hence, fast connections between two or more chip layers. On the other hand, TSVs consume a relative large amount of chip area and are error prone during manufacturing resulting in a dramatic yield drop for large TSV counts. Because of their short wire length, TSVs can be clocked much higher than conventional intra-layer links. To efficiently utilize the vertical bandwidth of TSVs, this paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. Virtual links can be state-of-the-art interconnects like busses, crossbars or 2D-NoC links. The TSV-Hub allows migration of traditional 2D interconnects towards the 3D stack while benefiting from a reduced TSV count and reuse of existing IP blocks and interconnection schemes. Furthermore, the TSV-Hub approach is also advantageous under interconnect resilience considerations. An incorporated switchbox enables dynamic protection switching for several faulty TSVs. Moreover, it can even cope with situations when more than the number of spare TSVs becomes defective. By means of a case study with two independent AXI interconnects, we could show an area reduction in the range of at least 10% for a TSV size of 10@mm and conservatively estimated the reliability improvement by one order of magnitude in comparison to a direct link interconnection.