A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks

Authors:
Thomas D. Richardson;Chrysostomos Nicopoulos;Dongkook Park;Vijaykrishnan Narayanan;Yuan Xie;Chita Das;Vijay Degalahal
Affiliations:
Pennsylvania State University;Pennsylvania State University;Pennsylvania State University;Pennsylvania State University;Pennsylvania State University;Pennsylvania State University;Pennsylvania State University
Venue:
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Year:
2006

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Abstract

The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-on-Chip(NoC). Both implementations have some inherent disadvantages — the former resulting from poor scalability and the transactional character of their operation, and the latter from inconsistent access times and deterioration of performance at high injection rates. In this paper, we propose a transaction-less, time-division-based bus architecture, which dynamically allocates timeslots on-the-fly — the dTDMA bus. This architecture addresses the contention issues of current bus architectures, while avoiding the multi-hop overhead of NoC's. It is compared to traditional bus architectures and NoC's and shown to outperform both for configurations with fewer than 10 PE's. In order to exploit the advantages of the dTDMA bus for smaller configurations, and the scalability of NoC's, we propose a new hybrid SoC interconnect combining the two, showing significant improvement in both latency and power consumption.