Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System Design with SystemC
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Digital Convergence
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Proceedings of the Conference on Design, Automation and Test in Europe
Capacity optimized NoC for multi-mode SoC
Proceedings of the 48th Design Automation Conference
Auto-design systematic methodology of cluster MPSoC for multiple concurrent applications
International Journal of Computer Applications in Technology
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The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper we present a framework to generate a dynamically reconfigurable crossbar-based on-chip communication architecture that can support multiple use-case bandwidth and latency constraints. Our framework generates on-chip communication architectures with a low cost, low power dissipation, and with minimal reconfiguration overhead. Results of applying our framework on several networking CMP applications show that our approach is able to generate a crossbar solution with significantly lower cost (2.4x to 3.8x), and lower power dissipation (1.5x to 3.1x), compared to the best previously proposed approach.