Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Latency-driven design of multi-purpose systems-on-chip
Proceedings of the 38th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Early analysis tools for system-on-a-chip design
IBM Journal of Research and Development
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplan driven leakage power aware IP-based SoC design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Applying stochastic modeling to bus arbitration for systems-on-chip
Integration, the VLSI Journal
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesisincludes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automaticallysynthesized for a network processor and a JPEG SoC.