Specification and design of embedded systems
Specification and design of embedded systems
The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Integrating communication protocol selection with partitioning in hardware/software codesign
Proceedings of the 11th international symposium on System synthesis
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Optimizing communication in embedded system co-simulation
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Performance Analysis of Systems with Multi-Channel Communication Architectures
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
COSMOS: a codesign approach for communicating systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A generic wrapper architecture for multi-processor SoC cosimulation and design
Proceedings of the ninth international symposium on Hardware/software codesign
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Parametric timing and power macromodels for high level simulation of low-swing interconnects
Proceedings of the 2002 international symposium on Low power electronics and design
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A high performance bus communication architecture through bus splitting
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
A continuous time markov decision process based on-chip buffer allocation methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Automatic network generation for system-on-chip communication design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of transaction level models for rapid design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Applying stochastic modeling to bus arbitration for systems-on-chip
Integration, the VLSI Journal
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multiobjective evolutionary algorithm-based optimisation model for network on chip synthesis
International Journal of Innovative Computing and Applications
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation
Proceedings of the 12th annual conference on Genetic and evolutionary computation
NoC-MPSoC performance estimation with synchronous data flow (SDF) graphs
AIS'11 Proceedings of the Second international conference on Autonomous and intelligent systems
Microprocessors & Microsystems
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In this paper, we present a methodology and efficient algorithms for the design of high-performance system-on-chip communication architectures. Our methodology automatically and optimally maps the various communications between system components onto a target communication architecture template that can consist of an arbitrary interconnection of shared or dedicated channels. In addition, our techniques simultaneously configure the communication protocols of each channel in the architecture in order to optimize system performance.We motivate the need for systematic exploration of the communication architecture design space, and highlight the issues involved through illustrative examples. We present a methodology and algorithms that address these issues, including the size and complexity of the design space. We present experimental results on example systems, including a cell forwarding unit of an ATM switch, that demonstrate the benefits of using the proposed techniques. Experimental results indicate that our techniques are successful in achieving significant improvements in system performance over conventional communication architectures (observed speedups over typical architectures such as single shared buses averaged 53%). Moreover, we demonstrate that our design space exploration methodology and optimization algorithms are efficient (low CPU times), underlining their usefulness as part of any system design flow.