Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Analyzing composability of applications on MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
MPSoC programming using the MAPS compiler
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
Multi-Processor Systems-on-Chip (MPSoC) are going to be the leading hardware platform featured in embedded systems, if they aren't already. This article deals with the performance estimation problem on these systems. We present in this paper, a new approach of performance estimation of migration software task to hardware component for MPSoC systems with Synchronous Data Flow (SDF) Graphs. This approach is structured on four steps: 1) annotation Kahn Process Network (KPN) model, 2) transformation the annotated KPN model to SDF model, 3) synthesis under constraints and 4) comparison of results. We have using the SDF3 tool to determine performance estimation of migration software task to hardware component. Experiments on MJPEG decoder are made to illustrate the efficiency of our approach of performance estimation.