DAC '97 Proceedings of the 34th annual Design Automation Conference
Dynamic communication models in embedded system co-simulation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Incorporating cores into system-level specification
Proceedings of the 11th international symposium on System synthesis
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Techniques for reducing read latency of core bus wrappers
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Experiments with the peripheral virtual component interface
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Interface Design for Core-Based Systems
IEEE Design & Test
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Scalable High-Performance DMA Architecture for DSP Applications
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Multi-Level Memory System Architecture for High-Performance DSP Applications
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A new approach to model communication for mapping and scheduling DSP-applications
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
High speed hardware-assisted real-time interprocess communication for embedded microcontrollers
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
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As the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms.