Computer networks
Specification and design of embedded systems
Specification and design of embedded systems
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Real-Time Systems Design and Analysis: An Engineer's Handbook
Real-Time Systems Design and Analysis: An Engineer's Handbook
Tiny Tera: A Packet Switch Core
IEEE Micro
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Guaranteeing the quality of services in networks on chip
Networks on chip
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A high performance bus communication architecture through bus splitting
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A continuous time markov decision process based on-chip buffer allocation methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving the scalability of SAMBA bus architecture
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Entry control in network-on-chip for memory power reduction
Proceedings of the 13th international symposium on Low power electronics and design
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scenario-oriented design for single-chip heterogeneous multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capacity metric for chip heterogeneous multiprocessors
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PROARTIS: Probabilistically Analyzable Real-Time Systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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This paper presents Lotterybus, a novel high-performance communication architecture for system-on-chip (SoC) designs. The Lotterybus architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of Lotterybus: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the Lotterybus architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4\% reduction in communication latencies over conventional on-chip communication architectures).