DAC '97 Proceedings of the 34th annual Design Automation Conference
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Adaptive Disk Spin-down Policies for Mobile Computers
MLICS '95 Proceedings of the 2nd Symposium on Mobile and Location-Independent Computing
A tool for describing and evaluating hierarchical real-time bus scheduling policies
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Fast Exploration of Bus-Based On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Policy optimization for dynamic power management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Surface wave communication system for on-chip and off-chip interconnects
Proceedings of the Fifth International Workshop on Network on Chip Architectures
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The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose FLEXBUS, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. FLEXBUS achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of FLEXBUS-based architectures. The techniques underlying FLEXBUS are general, and are applicable to a variety of bus standards. We have implemented FLEXBUS as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied FLEXBUS to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that FLEXBUS provides gains of up to 34.55% in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.