A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Simulation Environment for Core Based Embedded Systems
SS '97 Proceedings of the 30th Annual Simulation Symposium (SS '97)
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
RASoC: A Router Soft-Core for Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Network Processing Challenges and an Experimental NPU Platform
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
The routability of multiprocessor network topologies in FPGAs
Proceedings of the 2006 international workshop on System-level interconnect prediction
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
An architecture exploration environment for system on chip design
Nordic Journal of Computing
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN
Computers and Electrical Engineering
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serialized asynchronous links for NoC
Proceedings of the conference on Design, automation and test in Europe
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The modeling power of CINSim: Performance evaluation of interconnection networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
Routability of network topologies in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A routing algorithm for random error tolerance in network-on-chip
HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
Design of High-Radix Clos Network-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-CMP system with data communication on the fly
The Journal of Supercomputing
Inferring packet dependencies to improve trace based simulation of on-chip networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
3D NOC for many-core processors
Microelectronics Journal
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A generic packet router IP for multi-processors network-on-chip
Proceedings of the 8th FPGAWorld Conference
SMART: a single-cycle reconfigurable NoC for SoC applications
Proceedings of the Conference on Design, Automation and Test in Europe
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Area efficient asynchronous SDM routers using 2-stage clos switches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
Hi-index | 0.00 |
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.