A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Membership Test Logic for Delay-Insensitive Codes
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Electronic Notes in Theoretical Computer Science (ENTCS)
Relieving physical issues in new NoC-based SoCs
Proceedings of the 2nd international conference on Nano-Networks
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 7th ACM international conference on Computing frontiers
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same.