Performance Evaluation of Elastic GALS Interfaces and Network Fabric

Authors:
Junbok You;Yang Xu;Hosuk Han;Kenneth S. Stevens
Affiliations:
Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2008

Citing 7
Cited 3

Coping with Latency in SOC Design

IEEE Micro
Synchronous Interlocked Pipelines

ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Fourteen Ways to Fool Your Synchronizer

ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling

HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
GALS networks on chip: a new solution for asynchronous delay-insensitive links

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Synthesis of synchronous elastic architectures

Proceedings of the 43rd annual Design Automation Conference
Theory of latency-insensitive design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

The Future of Formal Methods and GALS Design

Electronic Notes in Theoretical Computer Science (ENTCS)
Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficiently one can synchronize into a clocked domain when elastic interfaces are utilized. Simulations show that the latency insensitive network allows excellent characterization of network performance in terms of the cost of routing, amount of blocking due to congestion, and message buffering. The network routers show that peak performance near 100% link utilization is achieved under congestion and combining. This enables accurate high-level modeling of the behavior of the network fabric so that optimized network design, including placement and routing, can occur through high-level network synthesis tools. The chip also shows that when elastic interfaces are used at the boundary of clock synchronization points then efficient domain crossings can occur. Buffering at the synchronization points are required to allow for variability in clocking frequencies and correct data transmission. The asynchronous buffering and synchronization scheme is shown to perform over four times faster than the clocked interface.