The Future of Formal Methods and GALS Design

Authors:
Kenneth S. Stevens;Daniel Gebhardt;Junbok You;Yang Xu;Vikas Vij;Shomit Das;Krishnaji Desai
Affiliations:
Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A;Electrical and Computer Engineering, University of Utah, Salt Lake City, U.S.A
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2009

Citing 26
Cited 1

Three partition refinement algorithms

SIAM Journal on Computing
An implementation of an efficient algorithm for bisimulation equivalence

Science of Computer Programming
Implementation of the data-flow synchronous language SIGNAL

PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
The Design and Use of Hazard-Free Switching Networks

Journal of the ACM (JACM)
Communication and Concurrency

Communication and Concurrency
Chain: A Delay-Insensitive Chip Area Interconnect

IEEE Micro
Relative timing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
FLEETzero: An Asynchronous Switching Experiment

ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Energy and Performance Models for Clocked and Asynchronous Communication

ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Practical verification and synthesis of low latency asynchronous systems

Practical verification and synthesis of low latency asynchronous systems
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling and Verifying Circuits Using Generalized Relative Timing

ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
GALS networks on chip: a new solution for asynchronous delay-insensitive links

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Efficient link capacity and QoS design for network-on-chip

Proceedings of the conference on Design, automation and test in Europe: Proceedings
A compositional behavioral modeling framework for embedded system design and conformance checking

International Journal of Parallel Programming
Synthesis of synchronous elastic architectures

Proceedings of the 43rd annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing application-specific networks on chips with floorplan information

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

IEEE Design & Test
A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE Micro
Performance Evaluation of Elastic GALS Interfaces and Network Fabric

Electronic Notes in Theoretical Computer Science (ENTCS)
Measuring deep metastability and its effect on synchronizer performance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
A methodology for constraint-driven synthesis of on-chip communications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Step persistence in the design of GALS systems

PETRI NETS'13 Proceedings of the 34th international conference on Application and Theory of Petri Nets and Concurrency

Quantified Score

Hi-index	0.00

Visualization

Abstract

The System-on-Chip era has arrived, and it arrived quickly. Modular composition of components through a shared interconnect is now becoming the standard, rather than the exotic. Asynchronous interconnect fabrics and globally asynchronous locally synchronous (GALS) design has been shown to be potentially advantageous. However, the arduous road to developing asynchronous on-chip communication and interfaces to clocked cores is still nascent. This road of converting to asynchronous networks, and potentially the core intellectual property block as well, will be rocky. Asynchronous circuit design has been employed since the 1950's. However, it is doubtful that its present form will be what we will see 10 years hence. This treatise is intended to provoke debate as it projects what technologies will look like in the future, and discusses, among other aspects, the role of formal verification, education, the CAD industry, and the ever present tradeoff between greed and fear.